1. Field of the Invention
The present invention relates generally to field effect type semiconductor devices and a manufacturing method therefor, and more particularly, to an improved LDDMOS (Lightly Doped Drain Metal Oxide Semiconductor) transistor and a manufacturing method therefor.
2. Description of the Background Art
A general structure of an initial field effect type MOS transistor comprises a pair of a source and a drain comprising diffusion layers of a conductivity type opposite to that of a semiconductor substrate formed at a given depth from the surface of the semiconductor substrate, and a gate comprising a conductive layer formed on the semiconductor substrate between the source and the drain through an insulating layer. In recent years, as a circuit device is miniaturized, the length between the source and the drain of the MOS transistor, that is, a channel length thereof is decreased. The MOS transistor having the above described structure accordingly presents the following problems.
An n channel MOS transistor will be described by way of example. When the n channel MOS transistor is rendered conductive, a channel occurs between a source and a drain of the n channel MOS transistor such that electrons flow from the source to the drain, that is, a drain current flows. On the other hand, a depletion layer exists in the vicinity of the drain, where the electric field strength is very high. Therefore, the electron-s which are the drain current are accelerated in the vicinity of the drain thereby to have high energy. Consequently, when the electrons having high energy collide with a crystal lattice, electrons are emitted (the electrons are referred to as hot electrons), resulting in ionization by collision by which an electron-hole pair is produced. In general, a positive potential is applied to a gate and the drain of the n channel MOS transistor and a negative potential is applied to a substrate thereof. Thus, the holes produced by ionization by collision flow into the side of the substrate while a part of the electrons produced flows into not the direction of the drain but the direction of the gate. As a result, electrons are trapped in the insulating layer formed under the gate so that the layer is negatively charged. Accordingly, there occur the problems in the use as a transistor, such as the change with time of a threshold voltage and the decrease in mutual conductance.
In order to solve the above described problems, an LDDMOS transistor has been developed. The LDDMOS transistor is currently used in a DRAM (Dynamic Random Access Memory) having a memory cell comprising a single transistor and a single capacitive device. An LDDMOS transistor currently known is disclosed in, for example, Japanese Patent Laying-Open Gazette Nos. 241375/1987 and 33470/1987 and an article entitled "Fabrication of High-Performance LDDFET'S with Oxide Sidewall-Spacer Technology", IE.sup.3 TRANSACTIONS ELECTRON DEVICE, Vol. ED-29, No. 4, Apr. 1982, pp. 590-596.
FIG. 5A is a cross sectional view showing a structure of the LDDMOS transistor described in the above described documents. Referring to FIG. 5, this LDDMOS transistor comprises a p-type semiconductor substrate 1, a gate electrode 2 formed on a major surface of the p-type semiconductor substrate 1 through a gate insulating film 3, sidewall insulating films (sidewalls) 4 formed on sidewalls of the gate electrode 2 and the gate insulating film 3, a pair of n-type diffusion layers 5a and 5b formed on the major surface of the semiconductor substrate 1 so as to extend to portions below side portions of the gate electrode 2, and a pair of n-type diffusion layers 6a and 6b formed on the major surface of the semiconductor substrate 1 so as to extend to portions below the sidewall insulating films 4 but not to extend to the portions below the side portions of the gate electrode 2. In addition, the impurity concentration of the n-type diffusion layers 5a and 5b is lower than that of the n-type diffusion layers 6a and 6b. A source region of this transistor corresponds to the n-type diffusion layers 5b and 6b. Thus, the LDDMOS transistor is characterized in that the source/drain region is formed of two diffusion layers having different impurity concentrations.
Description is now made of a method of manufacturing the LDDMOS transistor thus constructed with reference to FIGS. 5B and 5C. Referring now to FIG. 5B, a gate insulating film 3 is formed on a major surface of a p-type semiconductor substrate 1. In addition, a gate electrode 2 is formed on the gate insulating film 3. This gate electrode 2 is formed by forming conductive materials such as polysilicon (polycrystalline silicon) or a refractory metal on the major surface of the semiconductor substrate 1 and an entire surface of the gate insulating film 3 and then, selectively removing the same by reactive ion etching utilizing a plasma reaction. Referring now to FIG. 5C, n-type impurities such as arsenic (As) are ion-implanted into the major surface of the semiconductor substrate 1 at a concentration of approximately 1.times.10.sup.12 /cm.sup.2 to 1.times.10.sup.14 /cm.sup.2 by self-alignment utilizing the gate electrode 2 as a part of a mask. As a result, impurity diffusion layers of low concentration are formed at a given depth from the major surface of the semiconductor substrate 1 on both sides of the gate electrode 2. Thereafter, sidewall insulating films 4 are respectively formed on both sidewall of the gate electrode 2. The sidewall insulating films 4 are formed by first forming a silicon oxide film of a constant thickness on the gate electrode 2 and the major surface of semiconductor substrate 1 and then, removing the same by anisotropic etching such as ion etching until the surface of the gate electrode 2 is exposed. Thereafter, n-type impurities such as phosphorus (P) are ion-implanted into the major surface of the semiconductor substrate 1 at a concentration of 1.times.10.sup.14 /cm.sup.2 or more by self-alignment utilizing the gate electrode 2 and the sidewall insulating films 4 as a part of a mask. As a result, impurity diffusion layers of high concentration are formed at a given depth from the major surface of the semiconductor substrate 1 on both sides of the gate electrode 2. The implanted ions are then activated by heat treatment, so that respective one ends of the n-type diffusion layers 5a and 5b of low concentration extend to portions below side portions of the gate electrode 2 and respective one ends of the n-type diffusion layers 6a and 6b of high concentration extend to portions below side portions of the sidewall insulating films 4 but do not extend to the portions below the side portions of the gate electrode 2.
As described in the foregoing the source/drain regions of the LDDMOS transistor comprises the impurity diffusion layers of low concentration and the impurity diffusion layers of high concentration. Thus, referring to FIG. 5A, the length of extension of depletion layer which occurs in the vicinity of the drain in using the transistor becomes larger corresponding to a length .mu. of a deviation between the position of the impurity diffusion layer of low concentration and the position of the impurity diffusion layer of high concentration. Therefore, the electric field strength in the depletion layer of the LDDMOS transistor is decreased as compared with that of the conventional MOS transistor. As a result, the energy supplied to a drain current Id is decreased, the generation of hot electrons is suppressed and the electrons are not easily injected into the gate insulating film. However, the electric field strength in the vicinity of the n-type diffusion layers 5b and 6b constituting the drain is higher than that in the other portions. Thus, the amount of hot electrons generated in the vicinity of the drain is not zero but smaller than that of hot electrons generated in the vicinity of the drain of the conventional MOS transistor. On the other hand, the n-type diffusion layers 5b and 6b constituting the drain both extend to the portions below the sidewall insulating films 4. Therefore, the hot electrons generated are mainly trapped in the sidewall insulating films 4. The hot electrons trapped cancels and inverse the inherent polarity of the surface of the n-type diffusion layer 5b extending to the portions below the sidewall insulating films 4. Accordingly, the impurity concentration of the n-type diffusion layer 5b is effectively decreased. As a result, there occurs the problems of increasing the source resistance of the transistor and decreasing the mutual conductance gm or the like.
Furthermore, as the time period during which the transistor is used becomes longer, the amount of the hot electrons trapped in the sidewall insulating films 4 is increased. Accordingly, the effective impurity concentration of the n-type diffusion layer 5b is substantially decreased. As a result, a portion serving as the drain is only the n-type diffusion layer 6b of high concentration. This means that the drain does not extend to the portions below the gate electrode 2. As a result, a region of negative polarity which occurs under the electrode 2 by applying a positive voltage to the gate electrode 2 does not easily extend to the drain. More specifically, a channel does not easily occur between the source and the drain. Consequently, a voltage between the source and the gate. i. e., a threshold voltage V.sub.TH for rendering this transistor conductive is forced to be naturally increased. In addition, if the amount of hot electrons trapped in the sidewall insulating films 4 is further increased, a channel no longer easily occurs on the surface of the n-type diffusion layer 5b. That is, this transistor no longer functions as a transistor. As the result of an experiment, the above described problems become significant in manufacturing an n-channel transistor having a channel length of 1.2 .mu.m or less and a p-channel transistor having a channel length of 0.5 to 0.8 .mu.m or less. In order to solve the problems, an LDDMOS transistor adapted such that both diffusion layers of low concentration and high concentration constituting a pair of source drain regions to side portions of a gate electrode is disclosed in an article entitled "The Impact of Gate-Drain Overlapped LDD on VLSIs", Tech. Dig. of 1987 IE.sup.3 IEDM, Dec. 1987, pp. 38-41.
FIG. 6 is a cross-sectional view showing a structure of the above described LDDMOS transistor. Referring to FIG. 6, this LDDMOS transistor comprises a p-type semiconductor substrate 1, a gate electrode 2 formed on the semiconductor substrate 1 through a gate insulating film 3 and comprising a polysilicon layer 2a, an oxide film 2c of polysilicon, and a polysilicon layer 2b having a length and a width smaller than those of the polysilicon layer 2a, sidewall insulating films 7 in stepped portions of the polysilicon layers 2a and 2b, a pair of n-type diffusion layers 5a and 5b of low concentration formed on a major surface of the semiconductor substrate 1 so as to extend to portions below side portions of the polysilicon layer 2a and a pair of impurity diffusion layers 6a and 6b formed on the major surface of the semiconductor substrate 1 so as to extend to the major surface of the semiconductor substrate 1 below side portions of the polysilicon layer 2a but not to extend beyond the n-type diffusion layers 5a and 5b of low concentration. The oxide film 2c is an insulating layer whose thickness is very small. Thus, electric conduction is obtained between the polysilicon layers 2a and 2b with the oxide film 2c being interposed therebetween. Description is now made assuming that a source region of this transistor comprises the n-type diffusion layer 5a of low concentration and the n-type diffusion layer 6a of high concentration and the drain region thereof comprises the n-type diffusion layer 5b of low concentration and the n-type diffusion layer 6b of high concentration.
Description is now made of a method of manufacturing the LDDMOS transistor constructed as described above.
First, a gate insulating film 3 is formed on a major surface of a semiconductor substrate 1 and a polysilicon layer 2a having a sufficiently small thickness to transmit impurities is formed on this gate insulating film 3. The surface of this polysilicon layer 2a is oxidized, to form a very thin oxide film 2c. Then, polysilicon and a resist (not shown) having a desired pattern are sequentially formed over the oxide film 2c and the entire major surface of the semiconductor substrate 1 and removed by plasma etching utilizing the resist as a mask until the oxide film 2c is exposed, to form a polysilicon layer 2b. On this occasion, the oxide film 2c serves as a stopper for preventing the polysilicon layer 2a from being etched. n-type impurities of low concentration are then implanted into the major surface of the semiconductor substrate 1 utilizing the polysilicon layer 2a is sufficiently small to transmit impurities. Thus, n-type diffusion layers 5a and 5b of low concentration (represented by broken lines) are formed at a given depth from the major surface of the semiconductor substrate 1 below a portion, on which the polysilicon layer 2b is not formed, of the polysilicon layer 2a. Sidewall insulating films 7 are then formed in stepped portions of the polysilicon layers 2a and 2b. n-type impurities of high concentration are implanted into the major surface of the semiconductor substrate 1 utilizing as a mask the sidewall insulating films 7 and the polysilicon layer 2b. Consequently, n-type diffusion layers 6a and 6b of high concentration (represented by broken lines) are formed on both sides of the polysilicon layer 2a. Finally, the implanted impurity ions are activated by heat treatment so that respective one ends of the n-type diffusion layers 5a and 5b of low concentration and respective one ends of n-type diffusion layers 6a and 6b of high concentration extend in directions represented by arrows in FIG. 6. Consequently, the n-type diffusion layers 6a and 6b of high concentration are formed on the major surface of the semiconductor substrate 1 so as to extend to portions below side portions of the polysilicon layer 2a but not to extend beyond the n-type diffusion layers 5a and 5b of low concentration. More specifically, the n-type diffusion layers 5a and 5b of low concentration (represented by solid lines) and the n-type diffusion layers 6a and 6b of high concentration (represented by solid lines) are both overlapped with the portions below the gate electrode 2.
According to the LDDMOS transistor constructed as described above, one end of each of the diffusion layers 5a and 5b of low concentration and the diffusion layers 6a and 6b of high concentration constituting the source/drain region extends to the portions below the side portions of the lower polysilicon layer 2a constituting the gate electrode 2. Therefore, even if hot electrons generated and trapped in the gate insulating film 3 and the sidewall insulating films 7 causes the impurity concentration of the diffusion layer 5b to be effectively decreased so that the drain is effectively constituted by only the diffusion layer 6b, a channel is not prevented from being formed between the source and the drain.
The conventional LDDMOS transistor shown in FIG. 6 allows the problem caused by hot electrons to be solved. However, since the width and the length of the polysilicon layer 2b constituting the gate electrode 2 are made smaller than those of the lower polysilicon later 2a, the following problems are encountered in the manufacturing processes. In forming a polysilicon layer in the upper portion of the oxide film 2c and etching the same to form the polysilicon layer 2b, the oxide film 2c functions as an etching stopper. However, in order to cause the oxide film 2c to reliably function as the etching stopper, the thickness of the oxide film 2c must be increased to a certain extent. However, if the oxide film 2c is made too thick, electric conduction between the polysilicon layers 2a and 2b is degraded, so that the polysilicon layers 2a and 2b do not integrally function as the gate electrode 2. Contrary to this, if the oxide film 2c is made too thin so as to obtain electric conduction between the polysilicon layers 2a and 2b, the oxide film 2c does not function as an etching stopper. In order to cause the oxide film 2c to perform both the above described functions, the thickness thereof must be controlled to 10 to 20 .ANG.. It is substantially difficult to perform such control using the present manufacturing techniques. In addition, even if the thickness of the oxide film 2c can be controlled to be in the above described range, the oxide film 2c does not easily function as an etching stopper so long as etching precision at the time of formation of the polysilicon layer 2b is not increased.
Other examples of an LDDMOS transistor in which a source drain region is constituted by a double diffusion layer of high concentration and low concentration are disclosed in Japanese Patent Laying-Open Gazette Nos. 105868/1986 and 68657/1985. However, this LDDMOS transistor is only adapted such that diffusion is carried out utilizing the same mask two times, in forming an impurity layer of low concentration and an impurity layer of high concentration in the manufacturing processes thereof.
In addition, another example of an LDDMOS transistor in which a gate electrode has a two-layer structure and a source/drain region is constituted by a double diffusion layer of high concentration and low concentration is disclosed in Japanese patent Laying-Open Gazette No. 44790/1988. This LDDMOS transistor is adapted such that the width of an upper electrode portion constituting a gate electrode is larger than that of a lower electrode portion. Therefore, in the manufacture thereof, a thick oxide film layer exist between the upper electrode portion and a major surface of a semiconductor substrate. Accordingly, this LDDMOS transistor has the disadvantage in that a signal applied to the gate electrode is not easily transmitted to the semiconductor substrate due to the decrease in mutual conductance gm so that the force of on-off control of the MOS transistor is weakened.
Additionally, Japanese Patent Laying-Open Gazette No. 296740/1986 discloses an LDDMOS transistor in which an upper side portion of the cross section of a gate electrode is tapered so as to prevent disconnection of step portion of an aluminum interconnection layer on a gate electrode. Thus, the LDDMOS transistors in the above described four examples fail to solve the above described problems.